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VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes



  ID Publisher : 0000042301
  Nama Jurnal : International Journal of Electrical and Computer Engineering (IJECE)
  Pengarang : A. Boudaoud, M. El Haroussi, E. Abdelmounim
  Subjek : Error correcting codes, FPGA implementation, Interleaver, ML-DSC codes, Turbo decoding, VHDL language
  Edisi : 7 / 4 / Agustus 2017


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