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Fixed-Width Multiplier Circuits Using Column Bypassing and Decompositon Logic Techniques



  ID Publisher : 0000018451
  Nama Jurnal : International Journal on Electrical Engineering and Informatics (IJEEI)
  Pengarang : S. Balamurugan and P. S. Mallick
  Subjek : Fixed-width multipliers, low power, signed array multiplier, column bypassing, parallel architecture
  Edisi : 7 / 4 / 2015


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