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Clock Gated Single-Edge-Triggered Flip-Flop Design with Improved Power For Low Data Activity Applications



  ID Publisher : 0000018386
  Nama Jurnal : International Journal on Electrical Engineering and Informatics (IJEEI)
  Pengarang : Imran Ahmed Khan, Mirza Tariq Beg
  Subjek : Low power, CMOS digital integrated circuits, transition probability, edge Triggered, storage element, VLSI
  Edisi : 6 / 3 / 2014


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